A custom-0 MAC extension with a 64-bit saturating accumulator and Q15 read-out, built on a radix-4 Booth multiplier, integrated into a pipelined RV32IM processor and taken from Verilog to a routed FPGA with open-source tools.
synth_ecp5The MAC unit's two internal registers line up with the core's EX/MEM and MEM/WB registers, so a mac moves down the pipeline like any other instruction and writes back in WB.
| 0x0000_0000 | Instruction memory, 4 KiB, loaded from the program image |
| 0x0001_0000 | Data memory, 16 KiB, byte enables |
| custom-0 | mac msu mul.acc macu rdacc.lo rdacc.hi rdacc.q15 clracc |
rdacc.q15 turns Q30 into Q15 in one instruction.Cells from nextpnr coloured by block, over a copper routing-density map. The view opens framed on the logic; zoom out with − for the whole die and ⤢ to come back. Drag to pan, Ctrl/⌘ + scroll to zoom, hover a tile to see what is in it.
The unit testbenches compare against an independent reference model; the processor runs real RISC-V programs and compares every output sample bit by bit.
| Check | Result | Notes |
|---|---|---|
| Booth multiplier | 85,545 · 0 err | All 65,536 8-bit pairs, 34-bit corners and 20,000 random pairs |
| MAC unit testbench | 3,351 · 0 err | 13 test groups; scoreboard on rd, ACC, OVF and 2-cycle latency |
| Gate-level netlist | pass | Yosys netlist on the same testbench, zero-delay |
isa_test on the core | 18 / 18 | Every instruction class, forwarding, load-use and MAC-use stalls |
| FIR programs, 4 versions | 128 / 128 exact | Unwanted tone −60.1 dB against a design value of −60.2 dB |
| Mutation tests | all caught | Broken saturation, WB forwarding and stall logic each fail the tests |
Yosys check -assert | 0 issues | No latches, loops or undriven nets; 179 flip-flops match the RTL |
| Timing, core at 50 MHz target | 34.6 MHz | Critical path through the single-cycle RV32M multiplier |
A 16-tap Q15 low-pass FIR over 128 samples, measured with the core's cycle counters. All four versions produce the same bit-exact output.
One mac replaces the six-instruction 64-bit multiply-accumulate sequence, and rdacc.q15 replaces a 14-instruction shift-and-saturate routine.
The pipelined MAC unit is not the slowest path. It runs from WB forwarding, through the forwarding mux and the single-cycle RV32M multiplier on four DSP blocks, into EX/MEM; 18.9 ns of it is routing. Pipelining mul the way the MAC unit already is would be the next timing fix.
Separate 64-bit products for MUL, MULH, MULHSU and MULHU, plus a register file with a reset, made the first core 22,412 gates. One shared 33×33 multiplier and a reset-free register file in LUT-RAM brought it to 15,303 with identical results.
The Booth multiplier is most of the stand-alone MAC unit and the routing hot spot on the die. Yosys' own Booth and Wallace-tree generator saves 21 % of the gates but keeps the same 127-level depth, because the ripple-carry final adder sets it.
Post-increment loads and a hardware loop would let looped DSP code reach unrolled speed. After that: a parallel-prefix adder for the Booth multiplier, a pipelined RV32M multiplier, block-RAM memories and a run on a real ECP5 board.